XinAn PCB
PCB Impedance Control
Understanding and managing characteristic impedance for signal integrity
What is PCB Impedance Control?
Characteristic impedance (Z0) is the instantaneous ratio of voltage to current on a transmission line. In practical terms, every PCB trace carrying a signal above a few MHz behaves as a transmission line, and its impedance is determined by the trace geometry and the surrounding dielectric material. Z0 is not the same as DC resistance — it exists only for time-varying (AC) signals and depends on the distributed inductance and capacitance per unit length of the conductor.
When a signal source, transmission line, and termination all share the same impedance, maximum power transfer occurs with no reflections. When there is a mismatch — for example, a 50-ohm driver feeding a 75-ohm trace — part of the signal energy reflects back toward the source, causing ringing, overshoot, and degraded signal integrity. For modern high-speed buses (PCIe, DDR, USB, Ethernet), the transmission line impedance must be controlled to tight tolerances to meet the interface specification.
Impedance control in PCB manufacturing means that the fabricator guarantees the characteristic impedance of designated traces will fall within a specified tolerance, typically ±10%. This is achieved through controlled dielectric thickness, trace width management during etching, and material Dk consistency. The target impedance is modeled before production using field-solver software and verified after fabrication with TDR (Time Domain Reflectometry) measurements on test coupons.
Why Impedance Control Matters
Signal integrity problems — ringing, overshoot, timing jitter, crosstalk — are almost always rooted in impedance discontinuities. When a high-speed signal encounters a change in impedance (a connector transition, a via, or an uncontrolled trace width change), part of the signal reflects. The magnitude of the reflection is proportional to the impedance mismatch. In a multi-gigabit channel, even a 10% impedance deviation can push the eye diagram below the receiver threshold.
Controlled impedance is not optional for interfaces such as USB 2.0/3.x (90 ohm differential), HDMI (100 ohm differential), DDR4/5 (40 ohm single-ended), PCIe (85 ohm differential), and Ethernet (100 ohm differential). The interface specification defines the impedance value, and the PCB must deliver it. Failure to control impedance results in failed compliance testing, intermittent data errors, or EMI emissions that exceed regulatory limits.
Beyond digital interfaces, RF and microwave circuits are equally dependent on impedance matching. A 50-ohm microstrip feeding an antenna must hold its impedance across the operating band to maintain return loss and radiation efficiency. In these applications, impedance tolerance may need to be tighter than ±5%.
Factors Affecting Characteristic Impedance
| Parameter | Symbol | Effect on Impedance |
|---|---|---|
| Dielectric Constant | Er (εr) | Higher Er lowers impedance. FR-4 is typically 4.2-4.6; Rogers PTFE is 2.2-3.5. Er must be consistent across the panel for uniform impedance. |
| Dielectric Height | H | Distance between the trace and the reference plane. Increasing H raises impedance. Controlled by prepreg and core selection in the stackup. |
| Trace Width (Top) | W1 | The wider the trace, the lower the impedance. After etching, trace cross-section is trapezoidal — W1 is the top (narrower) width. |
| Trace Width (Bottom) | W2 | Bottom width of the etched trace. The difference between W1 and W2 (etch factor) affects impedance and must be accounted for in modeling. |
| Copper Thickness | T | Thicker copper slightly lowers impedance due to increased capacitance. Finished copper thickness after plating must be used in calculations. |
| Trace Spacing (Differential) | S | For differential pairs, closer spacing increases coupling and lowers differential impedance. Typical spacing is 1x to 2x the trace width. |
| Solder Mask Coating | C | Solder mask over traces adds a dielectric layer (Er ~3.3-3.8) that lowers impedance by 2-5 ohms. Must be included in the model for accuracy. |
Manufacturing Process Factors
Etching is the primary source of impedance variation. During the etch process, copper removal is not perfectly uniform across the panel. The edges of the panel may etch faster than the center, and inner-layer traces etch differently from outer-layer traces due to plating thickness variation. A typical outer-layer trace starts at the target width on the artwork, but after plating and etching, the finished width depends on the total copper thickness (base + plated), etch chemistry concentration, conveyor speed, and spray pressure. The result is a trapezoidal cross-section with an etch factor between 2:1 and 4:1.
To hold ±10% impedance tolerance, the factory must compensate the artwork trace width based on the expected etch loss, then verify the result on a test coupon. This compensation is calculated using impedance modeling software (Si9000 or Polar) with the actual material Dk, target dielectric thickness, and expected finished copper thickness as inputs. Consistent panel-to-panel etching requires tight chemical process control — etchant specific gravity, temperature, and spray nozzle maintenance are all monitored.
Impedance Calculation Methods
Impedance is calculated using electromagnetic field solvers that model the trace cross-section and surrounding geometry. The industry-standard tools are Polar Si8000 and Si9000, which implement 2D boundary-element methods validated against IPC-2141 and measured data. These tools accept the stackup parameters (Er, H, W1, W2, T, S, solder mask) and output the characteristic impedance for microstrip, stripline, coplanar, and differential configurations.
For initial design, engineers can use empirical formulas (Wheeler, Hammerstad-Jensen) or online calculators to estimate trace width for a target impedance. However, production impedance must be modeled with the actual laminate Dk data sheet value and the factory's stackup. We recommend that customers specify the target impedance and tolerance on the fabrication drawing, and let our engineering team calculate the required trace widths using Si9000 with our verified material and process data.
| Structure Type | Impedance | Description |
|---|---|---|
| Single-ended Microstrip | 50 Ω | Standard for RF and general-purpose single-ended routing. Used in coaxial-to-PCB transitions and test equipment. |
| Single-ended Stripline | 50 Ω | Inner-layer routing between two reference planes. Better shielding and lower radiation than microstrip. |
| Differential Microstrip | 90 Ω | USB 2.0 interface specification. Outer-layer differential pair with controlled spacing. |
| Differential Microstrip | 100 Ω | HDMI, Ethernet, LVDS, SATA, and most high-speed serial interfaces. |
| Differential Stripline | 100 Ω | PCIe, Ethernet, and high-speed serial links routed on inner layers for better noise isolation. |
| Differential Microstrip | 85 Ω | PCIe Gen3/Gen4/Gen5 specification for add-in card edge fingers. |
| Single-ended Microstrip | 40 Ω | DDR4/DDR5 data and address signals. Lower impedance for reduced voltage swing. |
Design Guidelines for Impedance Control
Start by identifying which nets require impedance control. Review the interface specification for the target impedance and tolerance. Group controlled-impedance nets by target value and pair type (single-ended vs. differential) so the PCB stackup can be optimized to support all targets simultaneously.
Mark impedance-controlled nets in your EDA tool with the appropriate constraint class. Set trace width and spacing rules based on the preliminary stackup. If you are designing a new stackup, coordinate with the fabricator early — the available prepreg and core thicknesses constrain which impedance values can be achieved at a given trace width. Designing to achievable trace widths (4-6 mil for outer layers, 3.5-5 mil for inner layers) is more manufacturable and cost-effective than pushing minimum widths.
On the fabrication drawing, specify: target impedance value, tolerance (±10% standard), trace layer, reference layer(s), and whether the traces are solder-mask-covered or exposed. If your design has multiple impedance targets, include a table listing each one. We will model the stackup, calculate compensated trace widths, and return a stackup proposal with impedance simulation results before production begins.
Impedance Test Coupon Design
Every impedance-controlled production panel includes test coupons at the panel border. The test coupon contains trace structures that replicate the controlled-impedance nets in the design — same layer, same width, same spacing, same reference plane distance. After fabrication, these coupons are measured with a TDR (Time Domain Reflectometry) instrument that sends a fast-edge pulse down the trace and reads the impedance profile.
The test coupon should include both single-ended and differential structures as needed, with a minimum trace length of 150mm for accurate TDR measurement. Coupons are measured on a sample basis per lot, and results are documented on the impedance test report shipped with the order. If any coupon measures out of tolerance, the panel is rejected and re-manufactured.
Our Impedance Control Capability
XinAn PCB provides ±10% impedance control as standard on all controlled-impedance orders, with ±5% available upon request for critical applications. We use Polar Si9000 field-solver software for pre-production impedance modeling and verify every lot with TDR coupon testing per IPC-TM-650 2.5.5.7. Our process engineers manage trace width compensation, etch uniformity, and dielectric thickness to deliver consistent impedance results across the full panel area. Impedance test reports with TDR waveforms are included with each shipment at no additional charge.